As the integration density of contemporary semiconductor memories continues to improve, there is a need for designs conducive to high yields, which are not overly complex and which do not compromise performance objectives. One critical memory parameter in high density designs is the bitline capacitance. As memories become smaller, the architectures should be designed with a reduced number of sense amplifier banks while preventing bitline capacitance and interbitline capacitance from becoming prohibitively large. The larger the bitline capacitance is relative to the storage cell capacitance, the lower is the storage cell signal at the input to the associated sense amplifier, and the higher the likelihood of data errors.
FIG. 1 illustrates a prior art DRAM architecture referred to as a full-length bitline architecture. Each sense amplifier (SA) is connected to one or two pairs of relatively long bitlines typically composed of tungsten. Each bitline connects to a large number of memory cells MC distributed along that bitline. For instance, sense amplifier SA.sub.i+1 in column (i+1) connects to true bitline BL.sub.(i+1)a and its complement BL.sub.(i+1)a on one side, and to true bitline BL.sub.i+1)b and complementary bitline BL.sub.(i+1)b on the other side. This is referred to as a"folded bitline architecture". As used herein, a column sometimes refers to a bitline pair. In some cases, a column refers to two adjacent bitlines. Isolation switches (not shown) on both sides of each sense amplifier are controlled to select which bitline group is to be written to or read from. Wordlines as WL.sub.j, WL.sub.j+1 running perpendicular to the bitlines connect to cells of a common row and selectively activate cells MC for data transfer and refresh operations. As shown in FIG. 2, each memory cell MC consists of a field effect transistor 12 and a storage capacitor C. As is well known, during a read operation, a wordline is activated to turn on the transistors 12 in a common row, thereby transferring charge stored on capacitor C to the bitline, or vice versa. The bitlines are precharged to a predetermined reference voltage (equalization voltage) prior to a read. As the charge is transferred between the capacitor and the associated bitline when a wordline is activated, that bitline's potential changes. If a cell coupled to a true bitline is being read from, the complementary bitline functions to provide the precharge reference voltage to the sense amplifier, and vice versa. Thus, a differential voltage is produced between the true and complementary lines when a cell is accessed. This differential voltage is amplified by the sense amplifier of the column to provide solid logic levels for data readout.
The bitline capacitance is proportional to the bitline length. As such, the bitline length is limited by the maximum bitline capacitance that can be tolerated. The maximum capacitance is generally determined by the allowable sensing margin and the power dissipation. Thus, in order to increase memory capacity by increasing the number of memory cells in an array, more sense amplifiers are needed for the array. Since sense amplifiers are relatively large, however, the chip size will correspondingly increase.
FIG. 3 schematically illustrates another prior art DRAM architecture, referred to as a hierarchical bitline architecture, which addresses some of the deficiencies of the above-described full-length bitline layout. This architecture is similar to a circuit configuration disclosed in U.S. Pat. No. Re. 33,694 entitled DYNAMIC MEMORY ARRAY WITH SEGMENTED BIT LINES. Each sense amplifier such as SA.sub.i is connected to a pair of master bitlines MBL and MBL (true and complementary, respectively). The master bitlines are composed of metal such as aluminum or tungsten. A number K of switches SW are connected between each master bitline such as MBL and K corresponding local bitlines LBL.sub.1 -LBL.sub.K of tungsten. Control lines 17.sub.1 -17.sub.K control the switch states of switches SW, where each control line activates or deactivates switches of a common row. The master bitlines are constructed in a different vertical layer than the local bitlines. A number of memory cells MC, typically up to several hundred, are connected to each local bitline. When a particular memory cell MC is to be accessed, the switch SW connected to the local bitline associated with that cell, e.g., to bitline LBL.sub.K, is switched on via a logic high applied to control line 17.sub.K. As such, only one local bit line pair LBL, LBL is connected to the master bitlines of the column and to the associated sense amplifier during read/write operations. Since each local bitline is shorter than in the full length architecture, its capacitance is less. The total bitline capacitance is then the sum of the local bitline capacitance and the master bitline capacitance. However, the master bitline capacitance per unit length is less than the local bitline capacitance per unit length since the local bitlines are directly coupled to a large number of memory cells, which significantly contribute to the local bitline capacitance, whereas the master bitlines are not directly coupled to the cells. Thus, for a given column length, the total capacitance can be significantly less than in the full length layout. Therefore, less space consuming sense amplifiers are needed for a chip with a specific number of memory cells. That is, the architecture permits each sense amplifier to be used for more cells, coupled to the local bitlines and one long master bitline, thereby reducing the number of sense amplifiers per chip. A smaller chip size is thus possible, provided that the area allocated to the switches SW and additional control circuitry does not exceed the area saved by reducing the number of sense amplifiers.
One drawback of the layout of FIG. 3 is that in each column, the master bitlines run the full length of the column such that master bitlines of adjacent columns such as C.sub.i, C.sub.i+1 run side by side. Hence, the master bitline (MBL) pitch, i.e., the periodic spacing between the centerlines of adjacent master bitlines, is essentially the same as the local bitline pitch. With high density memories, the MBL pitch is thus correspondingly small. This limits the yield of the memory as the likelihood of shorts between the closely spaced MBLs is significant. Also, the width of the MBLs must be kept narrow to provide adequate spacing between adjacent MBLs, which renders the fabrication process more difficult. Further, a close spacing between neighboring MBLs leads to higher interbitline capacitance, and thus, higher total MBL capacitance.
Another shortcoming of the architecture of FIG. 3 is the added complexity to the layout of the many bitline switches associated with each master bitline. The switches and their corresponding control lines occupy significant chip space and also render the fabrication process more difficult. Further, the attendant control and decoding circuitry needed to selectively activate and deactivate the large number of switches is complex and space consuming.
Accordingly, there is a need for a semiconductor memory architecture wherein bit line capacitance is kept low without an attendant overly complex layout, and which is conducive to a high yield.